1. Field of the Invention
This invention relates to an apparatus for the parallel processing of data. More particularly, the invention relates to a data parallel processing apparatus well-suited for application to an image processing system in which image data are processed at high speed and in parallel fashion by control of an image memory.
2. Related Art
When an image is processed at high speed, the general approach is to rely upon computer processing using software. However, higher processing speeds are required to deal with larger quantities of image data. There are two methods which can be adopted to raise processing speed. One is to rely upon sequential processing-type hardware or a so-called xe2x80x9cpipelinexe2x80x9d system. The other is to employ a parallel processing-type system in which a plurality of processors are arranged in parallel fashion. There is a limitation upon the image processing speed achievable with the former system since the clock frequency necessary for processing rises with an increase in the speed at which the picture data are processed. With the latter system, on the other hand, processing speed can be raised as much as desired by increasing the number of processors that are connected in parallel. In fact, speed can be maximized by providing a number of processors equivalent to the number of pixels. For this reason, the latter system represents a technique which is now the focus of much interest.
Here processing for communication between pixels takes on importance and it is necessary that processing proceed while such cross-communication is taking place. In the aforementioned parallel processing system, providing a number of processors equivalent to the number of pixels is impossible when dealing with high-resolution data. For example, when dealing with an image wherein a sheet of A4 size paper is read at 16 pixels/mm, the number of pixels is about 16M, and it would not be feasible to provide the system with this many processors simultaneously.
Accordingly, it is necessary to execute parallel processing using a finite, small number of processors. The specification of U.S. Ser. No. 807,662, filed on Dec. 11, 1985, proposes a technique for accomplishing such parallel processing, which involves dividing image data into a plurality of blocks each comprising plural items of image data, and processing the image data in each block by a respective one of a plurality of CPUs. The arrangement is such that each CPU receives an input of image data of the corresponding block as well as an input of image data of the adjoining blocks, and such that the CPU processes the image data of the corresponding block.
The proposed system still leaves room for improvement in terms of performance and construction.
A first object of the present invention is to provide a novel data parallel processing apparatus which represents an improvement of the prior art.
A second object of the present invention is to provide an image processing apparatus capable of executing image processing at high speed in a case where image information is processed by a plurality of processors.
A third object of the present invention is to provide an image processing apparatus capable of excellent spatial filtering processing in a case where image information is processed by a plurality of processors.
A fourth object of the present invention is to provide an image processing apparatus capable of excellent color processing in a case where image information is processed by a plurality of processors.
A fifth object of the present invention is to provide an image processing apparatus capable of excellent enlargement, reduction and rotation processing in a case where image information is processed by a plurality of processors.
According to the present invention, the foregoing objects are attained by-providing an image processing apparatus comprising an image memory and a processor unit. The image memory comprises a plurality of memory elements each capable of being addressed and accessed independently of other memory elements, wherein pixel data in each area of a plurality of areas obtained by dividing an image into the plurality of areas are assigned an identical address, and corresponding pixel data at identical positions in the areas are assigned to an identical one of the memory elements. The processor unit comprises a plurality of processor elements corresponding to the memory elements for simultaneously processing data of a plurality of pixels in the image memory. For example, the processor unit executes color conversion processing, image translating or image rotating.
Another object of the present invention is to provide a novel, efficient method of allotting image data to be processed by each processor in a case where image information is processed in a parallel by a plurality of processors.
In accordance with a preferred embodiment of the invention, this object is attained by providing a picture processing apparatus comprising an image memory and a processor unit. The image memory comprises a plurality of memory elements each capable of being addressed and accessed independently of other memory elements, wherein pixel data in each area of a plurality of areas obtained by dividing an image into the plurality of areas are assigned an identical address, and corresponding pixel data at identical positions in the areas are assigned to an identical one of the memory elements. The processor unit comprises a plurality of processor elements corresponding to the memory elements for simultaneously processing data of a plurality of pixels in the image memory. Thus, the pixel data in each area can be handled at high speed.
Still another object of the present invention is to provide an image processing apparatus adapted so as to execute complicated processing in a simple manner when image information is processed in parallel by a plurality of processors.
In accordance with a preferred embodiment of the invention, this object is attained by providing a picture processing apparatus comprising dividing means for dividing image data into a predetermined number of predetermined areas, and a plurality of processors the number whereof is equivalent to the number of divided areas, each processor having processor elements corresponding to the types of processing results.
A further object of the present invention is to provide an image processing apparatus adapted so as handle, in excellent fashion, input image information of a plurality of types.
Yet another object of the present invention is to provide a data parallel processing apparatus capable of processing a large quantity of data at high speed, in a multifunctional manner.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.